HS Code for Semiconductor Wafer: 3818.00 vs 8542 by Processing State

Semiconductor wafer imports power the US electronics manufacturing base. Despite the CHIPS Act expansion of domestic fab capacity, US consumption still relies heavily on Taiwanese, Korean, Japanese, and German wafer supply. The 2026 duty stack on wafers is favorable thanks to WTO ITA elimination of MFN. The classification split between bare wafer (3818) and patterned chip (8542) matters for documentation and origin determination.

This guide covers the 3818 vs 8542 split, the ITA framework, the active Section 301 treatment by subheading, and the CHIPS Act context.

Heading 3818 structure

HTS 3818.00 covers chemical elements doped for use in electronics, in the form of discs, wafers, or similar forms; chemical compounds doped for use in electronics. Most 300mm and 200mm bare silicon wafers classify here.

The subheading is relatively narrow:

• 3818.00.00: bare doped silicon wafers, compound semiconductor wafers, semiconductor-grade chemicals in disc form.

Statistical annotations may split by material (silicon vs SiC vs GaN vs GaAs) at the 10-digit level.

When does a wafer become an IC (chapter 85)?

The classification shifts when:

1. Photolithography has been performed to pattern circuit features.
2. The wafer carries identifiable integrated circuit devices (dies that would be singulated and packaged into chips).
3. The wafer has substantial value-add from device patterning, not just bare doped silicon.

Once these conditions are met, the wafer classifies in HTS 8542 (electronic integrated circuits). Specifically:

• 8542.90: un-singulated dies on wafer (before dicing), un-packaged dies, chiplets.
• 8542.31 / 32 / 33 / 39: packaged chips by function.

For most US importers, the bare wafer to chip transition happens at the foundry. Bare wafers shipped from a wafer producer (Shin-Etsu Japan, SUMCO Japan, Wacker Germany, Siltronic Germany, GlobalWafers Taiwan) to a foundry (TSMC, Samsung, Intel) classify as 3818. Patterned chips shipped from a foundry to a packager or end customer classify as 8542.

Worked example: Japanese bare wafer

500,000 USD of HTS 3818.00 polished 300mm silicon wafers from Shin-Etsu Japan.

Effective rate 7.1 percent. Section 122 is the only material duty layer on Japanese wafer imports.

Worked example: Taiwanese bare wafer

500,000 USD of HTS 3818.00 from GlobalWafers Taiwan.

Effective rate 5.1 percent. Taiwan is at the base Section 122 rate.

Worked example: Korean bare wafer

500,000 USD of HTS 3818.00 from SK Siltron Korea.

Effective rate 10.1 percent. KORUS waives the MFN duty but does NOT carve out Section 122, so Korean wafers still pay the 15 percent surcharge. Korean wafers remain a leading low-cost path on this HTS line because the absence of Section 301 (China-only) keeps the stack flat.

Worked example: Chinese bare wafer (silicon)

200,000 USD of HTS 3818.00 from a Chinese wafer producer.

Effective rate 17.3 percent. Chinese bare wafers do NOT carry the Section 301 layer that Chinese chips (8542) do, because USTR did not list 3818 on the same scope. Verify against the current USTR list.

This is one of the rare categories where Chinese origin lands cheaper than the equivalent chip from the same country (Chinese chips at 8542 stack to ~47 percent vs Chinese bare wafer at ~22 percent).

Worked example: Silicon carbide wafer from US (Wolfspeed) vs from China

US-origin SiC wafer from Wolfspeed New York is not imported (no duty).

For Chinese-origin SiC wafer (early stage industry in China): same treatment as silicon bare wafer above, approximately 22 percent landed cost.

CHIPS Act context

The CHIPS Act 2022 expanded US wafer production capacity:

• Silicon: existing producers (Sumco USA, GlobalWafers Texas expansion).
• Silicon carbide: Wolfspeed Mohawk Valley NY (largest SiC fab globally), Onsemi New Hampshire, II-VI.
• Gallium nitride: limited but expanding (BluGlass, Macom).
• Gallium arsenide / Indium phosphide: niche, Quest Innovations and IQE.

The act subsidizes domestic production via investment tax credits and grants. It does not impose import duties or restrictions on wafer imports. The practical effect for importers: more US-domestic wafer supply over the 2024-2030 period, reducing import dependency.

Documentation that supports the classification

• Wafer specification (diameter, thickness, doping type and level, crystal orientation, surface finish).
• Origin certificate (where the wafer was crystal-grown and polished).
• Test data sheet (resistivity, oxygen content, carbon content).
• For BIS export controls: ECCN classification if importing controlled items (advanced SiC, GaN, or other compound semiconductors may be controlled).

Run your wafer entry now

The LandedFees calculator handles 3818 with the WTO ITA framework, the Section 122 by country, the KORUS preference for Korean wafers, and the BIS Entity List flag for controlled materials.

Calculate a wafer entry

Section 122 status as of June 20 2026

The May 7 2026 Court of International Trade ruling in Oregon v. United States (consolidated with Burlap and Barrel v. United States) struck down the Section 122 proclamation. The Federal Circuit issued an administrative stay on May 12 2026, so CBP is still collecting the duty pending appeal. Importers paying now should preserve protest rights and refund claims in case the government loses on the merits. The underlying Section 122 authority sunsets July 24 2026 under the statutory 150-day ceiling, regardless of the appeal outcome, unless Congress extends or a fresh proclamation restarts the clock.

Citations

• USITC Harmonized Tariff Schedule heading 3818: https://hts.usitc.gov/?query=3818
• USITC Harmonized Tariff Schedule heading 8542: https://hts.usitc.gov/?query=8542
• WTO Information Technology Agreement: https://www.wto.org/english/tratop_e/inftec_e/inftec_e.htm
• USTR Section 301 lists
• CHIPS and Science Act 2022: https://www.commerce.gov/chips
• BIS Export Administration Regulations: https://www.bis.doc.gov