H341544

 HQ H341544 September 25, 2024 OT:RR:CTF:VS H341544 RRB CATEGORY: Origin John F. McKenzie Baker McKenzie Two Embarcadero Center, Suite 1100 San Francisco, CA 94111 RE: Country of Origin of an Analog Integrated Circuit Dear Mr. McKenzie: This is in response to your correspondence, dated April 4, 2024, on behalf of your client, 3PEAK, Inc. (“3PEAK”), requesting a ruling concerning the country of origin of an analog integrated circuit. FACTS: The merchandise at issue is an integrated circuit. 3PEAK states that the applications for its analog integrated circuits include communications, industrial, security monitoring, medical and healthcare, instrumentation, new energy and automotive. 3PEAK explains that its manufacture of analog integrated circuits occurs in three stages. Development of Semiconductor Circuit Designs in China In the first stage, 3PEAK’s engineers at its facilities in China develop the basic circuit design for its products, and convert that circuit design into a GDSII file. This file can be used by a semiconductor foundry to make photomasks as part of the production of circuitry on silicon wafers in the second stage of production. Front-End Processing in Japan or Taiwan During the second stage of manufacturing the analog integrated circuits, 3PEAK engages the services of third-party semiconductor foundries in Japan or Taiwan to manufacture the integrated circuits on semiconductor wafers. This stage involves the following steps: Epitaxial Wafer Production: This step consists of deposition, by means of epitaxial growth, of a thin film of semiconductor material on a bare silicon substrate. This epitaxial process perfects the crystal structure of the silicon substrate and improves its electrical characteristics. Oxidation: During oxidation, the silicon wafer is exposed to oxygen in a very high temperature furnace to produce a layer of silicon oxide on the surface of the wafer. This silicon oxide layer acts as an insulator and mask for further processing of the wafer. Thin-Film Deposition: By means of chemical vapor deposition, thin films of material are deposited on the silicon wafer. These thin film layers may act as structural layers of the integrated circuit or as separators between layers. Lithography: This is the process by which the circuit pattern of the integrated circuit is transferred from a mask to the surface of the silicon wafer. During this process, light-sensitive material, called a “photoresist,” is coated on the wafer and then exposed to ultraviolet light through a mask that contains the designed circuit pattern. Etching: Etching removes unwanted materials from the silicon wafer by exposing the wafer to a plasma of reactive gases, which removes material from exposed portions of the wafer. A particular silicon wafer will undergo multiple etchings of each layer in the manufacture of the integrated circuits on that wafer. Ion Implantation: During this step, the silicon wafer undergoes doping by introducing impurities into selected areas of the wafer in order to change its electrical characteristics. This step is performed by bombarding certain areas of the silicon wafer with a beam of selected high energy ions. Chemical Mechanical Planarization: Chemical mechanical planarization (“CMP”) is used to remove excess material from the wafer at several stages in the manufacturing process. CMP consists of “polishing” the wafer to remove material by chemical and mechanical means. Metal Wiring Process: Also referred to as “metallization,” this step involves forming interconnections between or among the layers of the integrated circuit. During this step, aluminum or copper is deposited on the surface of the silicon wafer by means of chemical vapor deposition. The metal layer is then patterned by means of photolithography and etching to create wires and contacts for connecting the various components and terminals of the integrated circuit. Wafer Testing: The final step in the front-end processing of the analog integrated circuit consists of testing the wafer to identify those integrated circuits on the wafer that are defective or damaged. 3PEAK states that after the front-end processing is complete, each of the 12,000 individual die on a single wafer produced in Japan has complete integrated circuit functionality, while each of the 36,000 individual die on a single wafer produced in Taiwan also has complete integrated circuit functionality. Back-End Processing in China Once front-end processing of the wafers in Japan or Taiwan is completed, the wafers are shipped to 3PEAK’s third-party semiconductor assembly and test entities (“OSATs”) in China for assembly of the wafers into finished integrated circuits. This stage involves the following steps: Bumping: Bumping involves forming a layer of copper pillars or “bumps” on the front surface of a semiconductor wafer to provide interconnection contact points for the individual die on a semiconductor wafer. Back Grinding: The packaging process begins with back grinding, during which the back side of the silicon wafer is thinned to allow for stacking and high-density packaging of integrated circuits. Wafer Sawing: The semiconductor wafer is cut into individual die, which can then be packaged into individual integrated circuits. Lead Frame Attachment: During this step, a lead frame, which is a thin layer of metal that provides external connection with circuitry of the die, is attached to each individual die. Wire Bond: During this step, gold wire is used to secure the connections between the lead frame and the packaging of the integrated circuit, in order to connect the integrated circuit to the printed circuit board to which it will be affixed. Molding: The assembled integrated circuit is encapsulated or packaged by coating the surfaces of each die with epoxy molding compound to seal the integrated circuit, which protects it from damage, moisture, and heat. Package Sawing: This step involves cutting the lead frame on each integrated circuit into a unit package. Final Testing: The finished integrated circuits undergo electrical testing before shipment in order to confirm that each integrated circuit is fully functional and meets 3PEAK’s specifications and requirements. ISSUE: What is the country of origin of the analog integrated circuit? LAW AND ANALYSIS: The United States Trade Representative (“USTR”) has determined that an additional ad valorem duty of 25 percent will be imposed on certain Chinese imports pursuant to its authority under Section 301(b) of the Trade Act of 1974 (“Section 301 measures”). The Section 301 measures apply to products of China enumerated in Section XXII, Chapter 99, Subchapter III, U.S. Note 20(f), HTSUS. When determining the country of origin for purposes of applying current trade remedies under Section 301, the substantial transformation analysis is applicable. The test for determining whether a substantial transformation will occur is whether an article emerges from a process with a new name, character, or use, different from that possessed by the article prior to processing. See Texas Instruments, Inc. v. United States, 69 C.C.P.A. 151 (1982). The substantial transformation determination is based on the totality of the evidence. See National Hand Tool Corp. v. United States, 16 CIT 308 (1992), aff’d, 989 F.2d 1201 (Fed. Cir. 1993). 3PEAK posits that the front-end processing steps that will occur either in Japan or Taiwan establish the essential character and use of the integrated circuits because the individual die on the semiconductor wafers manufactured in Japan or Taiwan will include complete integrated circuit functionality with pre-determined end uses. Moreover, 3PEAK states that none of the back-end processing steps occurring in China will change such character and use. Thus, 3PEAK asserts that the integrated circuits will not undergo a substantial transformation as a result of back-end processing in China. Accordingly, 3PEAK seeks confirmation that the count

The United States Trade Representative (“USTR”) has determined that an additional ad valorem duty of 25 percent will be imposed on certain Chinese imports pursuant to its authority under Section 301(b) of the Trade Act of 1974 (“Section 301 measures”). The Section 301 measures apply to products of China enumerated in Section XXII, Chapter 99, Subchapter III, U.S. Note 20(f), HTSUS. When determining the country of origin for purposes of applying current trade remedies under Section 301, the substantial transformation analysis is applicable. The test for determining whether a substantial transformation will occur is whether an article emerges from a process with a new name, character, or use, different from that possessed by the article prior to processing. See Texas Instruments, Inc. v. United States, 69 C.C.P.A. 151 (1982). The substantial transformation determination is based on the totality of the evidence. See National Hand Tool Corp. v. United States, 16 CIT 308 (1992), aff’d, 989 F.2d 1201 (Fed. Cir. 1993). 3PEAK posits that the front-end processing steps that will occur either in Japan or Taiwan establish the essential character and use of the integrated circuits because the individual die on the semiconductor wafers manufactured in Japan or Taiwan will include complete integrated circuit functionality with pre-determined end uses. Moreover, 3PEAK states that none of the back-end processing steps occurring in China will change such character and use. Thus, 3PEAK asserts that the integrated circuits will not undergo a substantial transformation as a result of back-end processing in China. Accordingly, 3PEAK seeks confirmation that the country of origin of its analog integrated circuits will be either Japan or Taiwan—depending on where the front-end processing occurs—since a substantial transformation will not occur as a result of back-end processing in China. In order to determine whether a substantial transformation occurs when components of various origins ar